1. Field of the Invention
This invention relates to a virtualization technology for using a physical core as a plurality of virtual cores, and more particularly, to a verification technology relating to a program operating on an arbitrary virtual core.
2. Description of the Related Art
In a recent information processing apparatus, a virtualization technology is used to build a plurality of virtual cores for use on a central processing unit (on a physical core) for executing programs.
The virtualization on the central processing unit is referred to as hardware multithreading technology and the like.
By the way, operation verification is carried out for various programs operating on the information processing apparatus by means of various methods.
When a program is debugged, a debugger is usually used for interactive investigation, or investigation is carried out based on static information by means of a memory dump. Any one of these methods influences a behavior of the program subject to the verification (hereinafter referred to as subject program), and is thus hard to use on an operating server or the like. Moreover, when an operating system (OS) itself is in a stalled state, and cannot be operated, the verification methods are further restricted.
If a function of referring to a state of a register or a memory by means of a function of hardware is provided in this case, the function is useful for the verification. The joint test action group (JTAG) and the in-circuit emulator (ICE) already exist as means for providing this function. On the other hand, the JTAG and the ICE are hardware apparatus which are not required for a normal operation, and are not currently implemented on a general server apparatus due to an increase in price and the like except for a special case for a developing application.
Moreover, information on the memory and the register is also accurately acquired from the information processing apparatus itself, and the information processing apparatus itself analyzes the information as the operation verification method for software.
The technologies relating to this invention are described in Japanese Patent No. 3206960, Japanese Unexamined Patent Application Publication (JP-A) No. 2003-085124, Japanese Unexamined Patent Application Publication (JP-A) No. 2008-310693, Japanese Patent No. 3867804, Japanese Patent No. 2577865, Japanese Patent No. 2868114, and Japanese Unexamined Patent Application Publication (JP-A) No. 2009-129101.
A central processing unit (CPU) which can read register information from the outside of a chip is proposed in each of Japanese Patent No. 3206960 and Japanese Unexamined Patent Application Publication (JP-A) No. 2003-085124. When the CPU reads a register content from the outside of the chip, register information copied in advance in a different area is read from the outside in order to avoid a cost for and complexity in synchronizing a register update by an execution context of the operating CPU and an external reference with each other.
Japanese Unexamined Patent Application Publication (JP-A) No. 2008-310693 and Japanese Patent No. 3867804 each propose a coprocessor for passing a register content from a main CPU to an extended arithmetic operation unit for continuing processing.
Moreover, Japanese Patent No. 2577865 proposes a method on a vector processor as an implementation method for sharing a register among CPUs. This is used when high-speed and high-capacity registers exist outside the CPUs, and vector arithmetic operation is carried out by sharing a register area among the plurality of CPUs and cores.
Moreover, Japanese Patent No. 2868114 proposes a method involving simultaneously operating a plurality of OSs on a set of pieces of hardware constituting a single information processing apparatus, and causing an OS for diagnosis to verify a value recorded by a program in a memory.
Moreover, Japanese Unexamined Patent Application Publication (JP-A) No. 2009-129101 describes a failure handling method for causing a plurality of CPUs to operate in parallel, and operating one CPU as a processor core for failure handling.
A memory dump, a debugger, a real time trace, and the like are used as the operation verification method for software.
The memory dump is a method of storing a memory image at a certain stop point of a subject program being executed so that a failure and the like are subsequently analyzed from a content of the memory image. Therefore, the memory dump has such an aspect as not being suitable for tracing a transition of the running location of the program and a change in data and other such analyses.
The debugger operates as if being able to analyze the operating subject program, but the subject program actually needs to be stopped while the debugger is operating, and hence the debugging has various types of influence on the processing operation by the subject program. Therefore, the debugger has such an aspect as not being suitable for analyzing a problem depending on operation timings of a plurality of programs or threads and the like.
Moreover, the debugger cannot be generally used when the OS is in the middle of startup processing, or the OS is stalled due to a certain failure. Moreover, such a kernel debugger as being used while the OS is stalled exists among kernel debuggers, but this is a method for analysis while the kernel is stopped, and hence the kernel debugger has such a problem that the entire OS stops. Therefore, there is such an aspect that the kernel debugger cannot easily be used as the verification method for a system in operation.
The real time trace is a technology of using hardware such as the JTAG and the ICE to investigate a state of a central processing unit (CPU) from the outside, and can be used even when an OS on which a subject program is running is stalled. On the other hand, dedicated expensive hardware needs to be independently implemented. Such hardware needs to be customized in terms of an operation frequency and the number of signals to be investigated depending on a subject circuit. Therefore, the real time trace is low in versatility. The JTAG is implemented on a CPU board in advance on some built-in apparatus, but such a demerit as the dedicated hardware built into the CPU board constituting a wasteful resource during a normal operation exists.
Moreover, in order to read consistent register information from the outside of the physical core on which the subject program is running regardless of an implementation form, the subject core needs to be temporarily stopped, and needs to transition to a debug mode, and then the register information needs to be transferred, and such a problem as a large overhead exists.
Moreover, the following points can be mentioned for describing problems in the operation verification method for software by using the exemplified related arts.
The CPU apparatus described in Japanese Patent No. 3206960 and Japanese Unexamined Patent Application Publication (JP-A) No. 2003-085124 can read register information copied to a different area in advance from the outside of the CPU board.
However, the register value referenced by the apparatus is a past content, and hence even if next analysis processing based on the read content is carried out, the CPU is already executing subsequent processing at this time point, and the CPU apparatus cannot be used for real time debugging.
The coprocessor described in Japanese Unexamined Patent Application Publication (JP-A) No. 2008-310693 and Japanese Patent No. 3867804 passes the register content from the main CPU to the extended arithmetic operation unit side for continuing processing.
However, the coprocessor is dedicated hardware intended to carry out a specific processing such as floating point arithmetic operation. The coprocessor has such a problem as requiring the form of additional provision, and also has a problem in a degree of freedom of the program for verification.
In the implementation method for sharing the register among the CPUs described in Japanese Patent No. 2577865, the high-speed and high-capacity registers needs to be provided outside the CPU. This configuration of the registers may be suitable for an expensive large-scale computer which can include a large amount of expensive memories.
However, the price highly tends to increase, and hence a current general architecture around the CPU cannot employ this configuration.
The verification method for application described in Japanese Patent No. 2868114 can check consistency of output results stored in the memory by the OS for diagnosis.
However, there is such a problem that the register value inside the CPU and the kernel cannot be analyzed.
The various operation verification methods for the subject program have been proposed as described above, but a method which can carry out real-time and detailed verification with less influence on the operation states of the subject program and the OS and less overhead is required.